Semiconductor devices

ABSTRACT

Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional patent application claims priority under 35U.S.C § 119 of Korean Patent Application No. 10-2017-0054567 filed onApr. 27, 2017 entire contents of which are hereby incorporated byreference.

BACKGROUND

The present inventive concept relates to semiconductor devices, and,more particularly, to semiconductor devices including an SRAM cell.

Semiconductor devices are widely used in the electronic industry due totheir compact size, multifunction, and/or low manufacturing cost. Thesemiconductor devices may include, on at least portions thereof, memorycells that store logic data.

The memory cells may include nonvolatile memory cells and volatilememory cells. A nonvolatile memory cell is characterized by the abilityto retain its stored data even when its power supply is interrupted. Forexample, a flash memory cell, a phase change memory cell, and a magneticmemory cell are all examples of nonvolatile memory cells. A volatilememory cell is characterized by losing its stored data when its powersupply is interrupted. For example, a static random access memory (SRAM)cell and a dynamic random access memory (DRAM) cell are all examples ofvolatile memory cells. An SRAM cell typically has low power consumptionand high operating speed in comparison with a DRAM cell.

An SRAM cell may be configured with a node contact between adjacent gatestructures. Typically, the node contact is spaced apart from theadjacent gate structures at approximately the same distance. The nodecontact is generally only designed to be electrically connected to oneof the two adjacent gate structures. In highly integrated memorydevices, however, the margins between the node contact and the adjacentgate structures may be small, which may increase the risk of electricalshorts between the node contact and an adjacent gate structure.

SUMMARY

Embodiments of the present inventive concept provide a semiconductordevice optimized for high integration.

Embodiments of the present inventive concept provide a semiconductordevice having improved electrical characteristics.

According to exemplary embodiments of the present inventive concept, asemiconductor device may comprise: a first active pattern and a secondactive pattern that extend in a first direction on a substrate and arespaced apart from each other in a second direction crossing the firstdirection; a first gate structure that extends across the first andsecond active patterns; a second gate structure that is spaced apartfrom the first gate structure; and a node contact between the first gatestructure and the second gate structure that electrically connects thefirst active pattern and the second active pattern to each other. Thenode contact may comprise a first end adjacent to the first activepattern and a second end adjacent to the second active pattern. Thesecond end of the node contact may he shifted in the first directionrelative to the first end of the node contact so as to be closer to thesecond gate structure than to the first gate structure.

According to exemplary embodiments of the present inventive concept, asemiconductor device may comprise: a first active pattern and a secondactive pattern that extend in a first direction on a substrate and arespaced apart from each other in a second direction crossing the firstdirection; a first gate structure that extends across the first andsecond active patterns; and a node contact on a side of the first gatestructure and electrically connects the first and second active patternsto each other. The node contact may comprise a first end adjacent to thefirst active pattern and a second end adjacent to the second activepattern. The first end of the node contact may be spaced apart from thefirst gate structure at a first distance. The second end of the nodecontact may be spaced apart from the first gate structure at a seconddistance greater than the first distance.

According to exemplary embodiments of the present inventive concept, asemiconductor device may comprise: a first gate structure on asubstrate; a second gate structure spaced apart in a first directionfrom the first gate structure; a third gate structure spaced apart inthe first direction from the first gate structure; and a node contactbetween the first gate structure and the second gate structure andbetween the first gate structure and the third gate structure. Thesecond and third gate structures may be aligned with each other in asecond direction crossing the first direction. The node contact maycomprise a first end between the first and third gate structures and asecond end between the first and second gate structures. The second endof the node contact may be shifted in the first direction relative tothe first end of the node contact so as to be closer to the second gate,structure than to the first gate structure.

It is noted that aspects of the inventive concepts described withrespect to one embodiment, may be incorporated in a different embodimentalthough not specifically described relative thereto. That is, allembodiments and/or features of any embodiment can be combined in any wayand/or combination. These and other aspects of the inventive conceptsare described in detail in the specification set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram illustrating a unit memory cellof a semiconductor device according to exemplary embodiments of thepresent inventive concept.

FIG. 2 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

FIG. 3 is an enlarged view corresponding to section A of FIG. 2.

FIGS. 4A to 4D are cross-sectional views respectively taken along linesI-I′, II-II′, III-III′, and IV-IV′ of FIG. 2.

FIGS. 5A to 9A are cross-sectional views corresponding to line I-I′ ofFIG. 2 illustrating a method of fabricating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept.

FIGS. 5B to 9B are cross-sectional views corresponding to line II-II′ ofFIG. 2 illustrating a method of fabricating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept.

FIGS. 5C to 9C are cross-sectional views corresponding to line III-III′of FIG. 2 illustrating a method of fabricating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept.

FIGS. 5D to 9D are cross-sectional views corresponding to line IV-IV′ ofFIG. 2 illustrating a method of fabricating a semiconductor deviceaccording to exemplary embodiments of the present inventive concept.

FIG. 10 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

FIG. 11 is a cross-sectional view taken along line II-II′ of FIG. 10.

FIG. 12 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

FIG. 13 is a cross-sectional view taken along line II-II′ of FIG. 12.

FIG. 14 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

FIG. 15 is an enlarged view corresponding to section B shown in FIG. 14.

FIG. 16 is a cross-sectional view taken along line V-V′ of FIG. 14.

FIG. 17 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present inventive concept will bedescribed in detail in conjunction with the accompanying drawings.

Some embodiments of the inventive concept stem from the realization thata semiconductor device, such as an SRAM cell, may be configured with anode contact between two adjacent gate structures. The node contact maybe electrically connected to one of the two adjacent gate structures insuch a manner that the end of the node contact that is electricallyconnected to one of the two gate structures is shifted in a directiontowards the gate structure to which it is connected relative to theother end of the node contact. By decreasing the distance between thenode contact and the gate structure to which it is electricallyconnected and increasing the distance between the node contact and thegate structure to which it is not electrically connected, the likelihoodof a short between the two gate structures may be reduced.

FIG. 1 is an equivalent circuit diagram showing a unit memory cell of asemiconductor device according to exemplary embodiments of the presentinventive concept.

Referring to FIG. 1, a semiconductor device may include an SRAM cell.The SRAM cell may include a first pull-up transistor TU1, a firstpull-down transistor TD1, a second pull-up transistor TU2, a secondpull-down transistor TD2, a first access transistor TA1, and a secondaccess transistor TA2. The first and second pull-up transistors TU1 andTU2 may be PMOS transistors. The first and second pull-down transistorsTD1 and TD2 and the first and second access transistors TA1 and TA2 maybe CMOS transistors.

The first pull-up and pull-down transistors TU1 and TD2 may each have afirst source/drain connected to a first node N1. The first pull-uptransistor TU1 may have a second source/drain connected to a power lineVcc, and the first pull-down transistor TD1 may have a secondsource/drain connected to a ground line Vss. The first pull-up andpull-down transistors TU1 and TD1 may have their gates electricallyconnected to each other. The first pull-up and pull-down transistors TU1and TD1 may constitute a first inverter. The first inverter may have aninput terminal corresponding to the connected gates of the first pull-upand pull-down transistors TU1 and TD1 and an output terminalcorresponding to the first node N1.

The second pull-up and pull-down transistors TU2 and TD2 may each have afirst source/drain connected to a second node N2. The second pull-uptransistor TU2 may have a second source/drain connected to the powerline Vcc, and the second pull-clown transistor TD2 may have a secondsource/drain connected to the ground line Vss. The second pull-up andpull-down transistors TU2 and TD2 may have their gates electricallyconnected to each other. The second pull-up and pull-down transistorsTU2 and TD2 may constitute a second inverter. The second inverter mayhave an input terminal corresponding to the connected gates of thesecond pull-up and pull-down transistors TU2 and TD2 and an outputterminal corresponding to the second node N2.

The first and second inverters may be mutually connected to constitute alatch structure. In this configuration, the gates of the first pull-upand pull-down transistors TU1 and TD1 may he electrically connected tothe second node N2, and the gates of the second pull-up and pull-downtransistors TU2 and TD2 may be electrically connected to the first nodeN1. The first access transistor TA1 may have a first source/drainconnected to the first node N1 and a second source/drain connected to afirst bit line BL1. The second access transistor TA2 may have a secondsource/drain connected to the second node N2 and a second source/drainconnected to a second bit line BL2. The first and second accesstransistors TA1 and TA2 may have their gates electrically connected to aword line WL. The circuit of FIG. 1 may, therefore, provide an SRAMcell.

FIG. 2 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept FIG. 3 is anenlarged view corresponding to section A of FIG. 2. FIGS. 4A to arecross-sectional views respectively taken along lines I-I′, II-II′,III-III′, and IV-IV′ of FIG. 2.

Referring to FIGS. 2 and 4A to 4D, a substrate 100 may be providedthereon with a device isolation layer ST that defines active patternsACT. The substrate 100 may be a semiconductor substrate. For example,the substrate 100 may be a silicon substrate, a germanium substrate, asilicon-germanium substrate, and/or a III-V group compound semiconductorsubstrate, The device isolation layer ST may include, for example, asilicon oxide layer. The active patterns ACT may extend in a firstdirection D1 and be spaced apart from each other in a second directionD2. The active patterns ACT may protrude from the substrate 100 and beseparated from each other by the device isolation layer ST. Each of theactive patterns ACT may have an upper portion (referred to hereinafteras an active fin AF) exposed by the device isolation layer ST.

The substrate 100 may include a PMOSFET region PR, a first NMOSFETregion NR1, and a second NMOSFET region NR2. The first and secondNMOSFET regions NR1 and NR2 may be separated from each other across thePMOSFET region PR. The first and second NMOSFET regions NR1 and NR2 maybe spaced apart from each other in the second direction D2. The activepatterns ACT may include first active patterns ACT1 provided on thefirst and second NMOSFET regions NR1 and NR2 and second active patternsACT2 provided on the PMOSFET region PR. The first active patterns ACT1may have a conductive type different from that of the second activepatterns AC12. A single first active pattern ACT1 may be provided oneach of the first and second NMOSFET regions R1 and NR2, but embodimentsof the present inventive concept are not limited thereto. Differentlyfrom those shown in figures, a plurality of the first active patternsACT1 may he provided on each of the first and second NMOSFET regions NR1and NR2. A pair of the second active patterns ACT2 may be provided onthe PMOSFET region PR, but embodiments of the present inventive conceptare not limited thereto.

The substrate 100 may he provided thereon with gate structures GSrunning across the active patterns AP. Each of the gate structures GSmay extend in the second direction D2 and cover top and side surfaces ofthe active fin AF of each active pattern ACT. The gate structures GS mayinclude a first gate structure GS1, a second gate structure GS2, a thirdgate structure GS3, and a fourth gate structure GS4 that arehorizontally spaced apart from each other. The first gate structure GS1may be spaced apart in the first direction D1 from the second gatestructure GS2. The third gate structure GS3 may be aligned in the seconddirection D2 with the second gate structure GS2, and the first gatestructure GS1 may be spaced apart in the first direction D1 from thethird gate structure GS3. The fourth gate structure GS4 may be alignedin the second direction D2 with the first gate structure GS1 and spacedapart in the first direction D1 from the second gate structure GS2. Thefirst and second gate structures GS1 and GS2 may be spaced at a pitchthe same as that between the first and third gate structures GS1 and GS3and that between the second and fourth gate structures GS2 and GS4.

The first gate structure GS1 may extend across the first NMOSFET regionNR1 and the PMOSFET region PR, and the second gate structure GS2 mayextend across the second NMOSFET region NR2 and the PMOSFET region PR.The third and fourth gate structures GS3 and GS4 may be providedrespectively on the first and second NMOSFET regions NR1 and NR2. Eachof the first and third gate structures GS1 and GS3 may extend across thefirst active pattern ACT1 on the first NMOSFET region NR1. The firstgate structure GS1 may extend onto the PMOSFET region PR and extendacross one of the second active patterns ACT2 that is adjacent to thefirst NMOSFET region NR1. The first gate structure GS1 may partiallyoverlap another of the second active patterns ACT2 that is separatedfrom the first NMOSFET region NR1. Each of the second and fourth gatestructures GS2 and GS4 may extend across the first active pattern ACT1on the second NMOSFET region NR2. The second gate structure GS2 mayextend onto the PMOSFET region PR and extend across one of the secondactive patterns ACT2 that is adjacent to the second NMOSFET region NR2.The second gate structure GS2 may partially overlap another of thesecond active patterns ACT2 that is separated from the second NMOSFETregion NR2.

Each of the gate structures GS may include a gate electrode GE extendingin the second direction D2, a gate dielectric pattern GI extending alonga bottom surface of the gate electrode GE, a capping pattern CAPextending along a top surface of the gate electrode GE, and gate spacersGSP on sidewalls of the gate electrode GE. The gate dielectric patternGI may extend between the gate electrode GE and the gate spacers GSP.The gate electrode GE may include a conductive material. For example,the gate electrode GE may include one or more of a doped semiconductorand a conductive metal nitride. The gate dielectric pattern GI mayinclude a silicon oxide layer, a silicon oxynitride layer, or a high-kdielectric layer whose dielectric constant is greater than that of asilicon oxide layer. Each of the capping pattern CAP and the gatespacers GSP may include one or more of a silicon oxide layer, a silicon,nitride layer, and/or a silicon oxynitride layer.

Source/drain regions SD may be provided on the active patterns ACT atopposite sides of each gate structure GS. The source/drain regions SDmay include epitaxial layers grown from the active patterns ACT servingas seeds. The source/drain regions SD may include one or more of silicongermanium (SiGe), silicon (Si), and/or silicon carbide (SiC). Each ofthe source/drain regions SD may further include impurities. Thesource/drain regions SD on the PMOSFET region PR may include P-typeimpurities, and the source/drain regions SD on the first and secondNMOSFET regions NR1 and NR2 may include N-type impurities. Each of theactive patterns ACT may include the active fin AF that is provided belowthe gate structure GS and between the source/drain regions SD. Theactive fin AF may be used as a channel region.

The first gate structure GS1 and the first active pattern ACT1 extendingthereacross may constitute a first pull-down transistor. The first gatestructure GS1 and the second active pattern ACT2 extending thereacrossmay constitute a first pull-up transistor. The third gate structure GS3and the first active pattern ACTT extending thereacross may constitute afirst access transistor. The second gate structure GS2 and the firstactive pattern ACT1 extending thereacross may constitute a secondpull-down transistor. The second gate structure GS2 and the secondactive pattern ACT2 extending thereacross may constitute a secondpull-up transistor. The fourth gate structure GS4 and the first activepattern ACT1 extending thereacross may constitute a second accesstransistor. The aforementioned six transistors may constitute the SRAMcell described with reference to FIG. 1.

The substrate 100 may be provided thereon with a first interlayerdielectric layer 170 that covers the gate structures GS and thesource/drain regions SD. The gate structures GS may have top surfacescoplanar with a top surface of the first interlayer dielectric layer170. A second interlayer dielectric layer 180 may be provided on thefirst interlayer dielectric layer 170. Each of the first and secondinterlayer dielectric layers 170 and 180 may include, for example, oneor more of a silicon oxide layer, a silicon nitride layer, a siliconoxynitride layer, or a low-k dielectric layer.

The substrate 100 may be provided thereon with source/drain contacts 150and node contacts 155. The source/drain contacts 150 and the nodecontacts 155 may each be provided to penetrate the first and secondinterlayer dielectric layers 170 and 180. Each of the source/draincontacts 150 may be connected to a corresponding one of the source/drainregions SD. The node contacts 155 may include a first node contact 155 aextending across the first NMOSFET region NR1 and the PMOSFET region PRand a second node contact 155 b extending across the second NMOSFETregion NR2 and the PMOSFET region PR. The first node contact 155 a mayelectrically connect a corresponding source/drain region SD on the firstNMOSFET region NR1 to a corresponding source/drain region SD on thePMOSFET region PR. The first node contact 155 a may extend onto thedevice isolation layer ST between the first NMOSFET region NR1 and thePMOSFET region PR. The second node contact 155 b may electricallyconnect a corresponding source/drain region SD on the second NMOSFETregion NR2 to a corresponding source/drain region SD on the PMOSFETregion PR. The second node contact 155 b may extend onto the deviceisolation layer ST between the second NMOSFET region NR2 and the PMOSFETregion PR.

Referring to FIGS. 2 and 3, the first node contact 155 a may be providedbetween the first and third gate structures GS1 and GS3 and between thefirst and second gate structures GS1 and GS2. The first node contact 155a may overlap the first active pattern ACT1 on the first NMOSFET regionNR1, and extend onto the PMOSFET region PR to overlap one of the secondactive patterns ACT2 that is adjacent to the first NMOSFET region NR1.The first node contact 155 a may include a first end EP1 and a secondend EP2 opposite to each other. For example, the first end EP1 may be aportion of the first node contact 155 a, which is provided on the firstNMOSFET region NR1, and the second end EP2 may be another portion of thefirst node contact 155 a, which is provided on the PMOSFET region PR.The first end EP1 may adjoin the first active pattern ACT1 on the firstNMOSFET region NR1, and the second end EP2 may adjoin the second activepattern ACT2 adjacent to the first NMOSFET region NR1.

The first end EP1 may be spaced apart at a first distance d1 from eachof the first and third gate structures GS1 and GS3. The second end EP2may laterally shift from the first end EP1 to lie closer to the secondgate structure GS2 than to the first gate structure GS1. The second endEP2 may be spaced apart from the first gate structure GS1 at a seconddistance d2 greater than the first distance d1. The second end EP2 maybe spaced apart from the second gate structure GS2 at a third distanced3 less than the first and second distances d1 and d2. Each of the firstto third distances d1, d2, and d3 may be measured in the first directionD1. The first node contact 155 a may have, as viewed in plan, a bentline shape extending in the second direction D2. For example, as viewedin plan, the first node contact 155 a may have a non straight line shapeCS in which at least a portion of the first node contact 155 a is curvedto allow the second end EP2 to adjoin the second gate structure GS2.

Referring back to FIGS. 2 and 4A to 4D, the second node contact 155 bmay be provided between the second and fourth gate structures GS2 andGS4 and between the first and second gate structures GS1 and GS2. Thesecond node contact 155 b may overlap the first active pattern ACT1 onthe second NMOSFET region NR2, and extend onto the PMOSFET region PR tooverlap one of the second active patterns ACT2 that is adjacent to thesecond NMOSFET region NR2. The second node contact 155 b may have ashape symmetrical to that of the first node contact 155 a. The secondnode contact 155 b may include a first end provided on the secondNMOSFET region NR2 and a second end provided on the PMOSFET region PR.The first end of the second node contact 155 b may adjoin the firstactive pattern ACT on the second NMOSFET region NR2, and the second endof the second node contact 155 b may adjoin the second active patternACT2 adjacent to the second NMOSFET region NR2. The first end of thesecond node contact 155 b may be spaced apart at the first distance d1from each of the second and fourth gate structures GS2 and GS4. Thesecond end of the second node contact 155 b may laterally shift from thefirst end of the second node contact 155 b to lie closer to the firstgate structure GM than to the second gate structure GS2. The second endof the second node contact 155 b may be spaced apart at the seconddistance d2 from the second gate structure GS2 and at the third distanced3 from the first gate structure GS1.

Gate contacts 160 may be provided on the gate structures GS. Each of thegate contacts 160 may penetrate the second interlayer dielectric layer180 and be connected to the gate electrode GE of each gate structure GS.The gate contact 160 on the second gate structure GS2 may overlap thefirst node contact 155 a in a plan view. The gate contact 160 on thesecond gate structure GS2 may be connected to the first node contact 155a and the gate electrode GE of the second gate structure GS2.Accordingly, the gate electrode GE of the second gate structure GS2 maybe electrically connected to the substrate 100 through the gate contact160 and the first node contact 155 a. That is, the gate electrode GE ofthe second gate structure GS2 may be electrically connected to the firstand second active patterns ACT1 and ACT2 that are mutually connectedthrough the first node contact 155 a. The gate contact 160 on the firstgate structure GS1 may overlap the second node contact 155 b in a planview. The gate contact 160 on the first gate structure GS1 may beconnected to the second node contact 155 b and the gate electrode GE ofthe first gate structure GS1. Accordingly, the gate electrode GE of thefirst gate structure 051 may be electrically connected to the substrate100 through the gate contact 160 and the second node contact 1551. Thatis, the gate electrode GE of the first gate structure GS1 may beelectrically connected to the first and second active patterns ACT1 andACT2 that are mutually connected through the second node contact 155 b.It may, therefore, be possible to provide the latch structure of theSRAM cell discussed with reference to FIG. 1.

The source/drain contacts 150, the node contacts 155, and the gatecontacts 160 may have their top surfaces substantially coplanar with atop surface of the second interlayer dielectric layer 180. Thesource/drain contacts 150, the node contacts 155, and the gate contacts160 may include the same conductive material. The source/drain contacts150, the node contacts 155, and the gate contacts 160 may include, forexample, one or more of a doped semiconductor, a metal, and a conductivemetal nitride. Although not shown, the second interlayer dielectriclayer 180 may be provided thereon with electrical lines that areelectrically connected to the source/drain contacts 150 and the gatecontacts 160. The electrical lines may provide the source/drain regionsSD and the gate electrodes GE with voltages through the source/draincontacts 150 and the gate contacts 160.

The increase in integration of semiconductor devices may problematicallycause electrical shorts between gate electrodes and their adjacent nodecontacts constituting SRAM cells.

According to some embodiments of the present inventive concept, thefirst node contact 155 a (or the second node contact 155 b) may includethe first end EP1 and the second end EP2 laterally shifted from thefirst end EP1. In this configuration, the first node contact 155 a maybe positioned closer to a specific gate structure than to its adjacentgate structures. The first node contact 155 a may be electricallyconnected through the gate contact 160 to the specific gate structure,and spaced apart at a desired distance from the adjacent gatestructures. As a result, electrical shorts may be prevented, reduced, orminimized between the first node contact 155 a and the adjacent gatestructures.

FIGS. 5A to 9A are cross-sectional views corresponding to line of FIG. 2illustrating a method of fabricating a semiconductor device according toexemplary embodiments of the present inventive concept. FIGS. 5B to 9Bare cross-sectional views corresponding to line of FIG. 2 illustrating amethod of fabricating a semiconductor device according to exemplaryembodiments of the present inventive concept. FIGS. 5C to 9C arecross-sectional views corresponding to line of FIG. 2 illustrating amethod of fabricating a semiconductor device according to exemplaryembodiments of the present inventive concept. FIGS. 5D to 9D arecross-sectional views corresponding to line IV-IV′ of FIG. 2illustrating a method of fabricating a semiconductor device according toexemplary embodiments of the present inventive concept.

Referring to FIGS. 2 and 5A to 5D, a substrate 100 may be patterned toform trenches T defining active patterns ACT. The active patterns ACTmay extend in the first direction D1 and be spaced apart from each otherin the second direction D2. The formation of the trenches T may includeforming mask patterns (not shown) on the substrate 100 andanisotropically etching the substrate 100 using the mask patterns as anetch mask. A device isolation layer ST may be formed to fill thetrenches T. The formation of the device isolation layer ST may includeforming on the substrate 100 an insulation layer to fill the trenches Tand planarizing the insulation layer until the mask patterns areexposed. An upper portion of the device isolation layer ST may berecessed to expose an upper portion of each active pattern ACT. Theexposed upper portion of each active pattern ACT may be defined as anactive fin AF. When the upper portion of the device isolation layer STis recessed, the mask patterns may be removed and top surfaces of theactive patterns ACT may be exposed.

The substrate 100 may include a PMOSFET region PR, a first NMOSFETregion NR1, and a second NMOSFET region NR2. The first and secondNMOSFET regions NR1 and NR2 may be separated from each other across thePMOSFET region PR. The device isolation layer ST may be formed to havesubstantially the same depth in a direction perpendicular to a topsurface of the substrate 100. Alternatively, the device isolation layerST may be formed to have portions, between the PMOSFET region PR and thefirst NMOSFET region NR1 and between the PMOSFET region PR and thesecond NMOSFET region NR2, whose depths are greater than those of otherportions thereof.

The active patterns ACT may include first active patterns ACT1 providedon the first and second NMOSFET regions NR1 and NR2 and second activepatterns ACT2 provided on the PMOSFET region PR. The first activepatterns ACT1 may have a conductivity type different from that of thesecond active patterns ACT2.

Referring to FIGS. 2 and 6A to 6D, sacrificial gate structures SGS maybe formed on the substrate 100 to extend across the active patterns ACT.Each of the sacrificial gate structures SGS may extend in the seconddirection D2. As viewed in plan, an arrangement of the sacrificial gatestructures SGS may be the same as that of the gate structures GSdiscussed with reference to FIGS. 2 and 4A to 4D. Each of thesacrificial gate structures SGS may include, an etch stop pattern 102, asacrificial gate pattern 110, and a sacrificial mask pattern 112 thatare sequentially stacked on the substrate 100. Each of the sacrificialgate structures SGS may further include gate spacers GSP on side wallsof the sacrificial gate pattern 110.

The formation of the sacrificial gate structures SGS may includesequentially forming an etch stop layer and a sacrificial gate layer onthe substrate 100, forming the sacrificial mask pattern 112 on thesacrificial gate layer, and patterning the sacrificial gate layer andthe etch stop layer using the sacrificial mask pattern 112 as an etchmask. The etch stop layer may include, for example, silicon oxide. Thesacrificial gate layer may include a material exhibiting an etchselectivity with respect to the etch stop layer. The sacrificial gatelayer may include, for example, polysilicon. The sacrificial maskpattern 112 may include a material exhibiting an etch selectivity withrespect to the sacrificial gate layer. The sacrificial mask pattern 112may include, for example, silicon nitride. The sacrificial gate layerand the etch stop layer may he patterned to respectively form thesacrificial gate pattern 110 and the etch stop pattern 102. After thesacrificial gate pattern 110 and the etch stop pattern 102 are formed,the gate spacers GSP may be formed on the sidewalls of the sacrificialgate pattern 110. The formation of the gate spacers GSP ma includeforming on the substrate 100 a gate spacer layer to cover thesacrificial mask pattern 112, the sacrificial gate pattern 110, and theetch stop pattern 102 and then performing an anisotropic etching processon the gate spacer layer. The gate spacer layer may include, forexample, silicon nitride. The anisotropic etching process of the gatespacer layer may expose the active patterns ACT at opposite sides ofeach sacrificial gate structure SGS and a top surface of the deviceisolation layer ST at opposite sides of each sacrificial gate structureSGS. The anisotropic etching process of the gate spacer layer mayfarther expose a top surface of the sacrificial mask pattern 112 of eachsacrificial gate structure SGS.

Source/drain regions SD may be formed on the active patterns ACT atopposite sides of each sacrificial gate structure SGS. The formation ofthe source/drain regions SD may include performing a selective epitaxialgrowth process on the substrate 100. The source/drain regions SD mayinclude one or more of silicon germanium, (SiGe), silicon (Si), andsilicon carbide (SiC), which can be grown from the active patterns ACTserving as seeds. The source drain regions SD may be doped withimpurities either simultaneously with or after the epitaxial process.The source/drain regions SD on the PMOSFET region PR may include P-typeimpurities, and the source/drain regions SD on the first and secondNMOSFET regions NR1 and NR2 may include N-type impurities. Each of theactive patterns ACT may include the active fin AF that is provided belowthe sacrificial gate structure SOS and between the source/drain regionsSD. The active fin AF may be used as a channel region.

A first interlayer dielectric layer 170 may then be formed on thesubstrate 100. The first interlayer dielectric layer 170 may cover thesacrificial gate structures SGS and the source/drain regions SD. Thefirst interlayer dielectric layer 170 may include, for example, one ormore of a silicon oxide layer, a silicon nitride layer, a siliconoxynitride layer, and a low-k dielectric layer.

Referring to FIGS. 2 and 7A to 7D, an upper portion of the firstinterlayer dielectric layer 170 may be etched to expose a top surface ofthe sacrificial gate pattern 110 of each sacrificial gate structure SGS.When the first interlayer dielectric layer 170 is etched, thesacrificial mask pattern 112 of each sacrificial gate structure SGS andupper portions of the gate spacers GSP may be removed. Thereafter, thesacrificial gate pattern 110 may be removed from each of the sacrificialgate structures SGS. Accordingly, a gap 190 may be formed between thegate spacers GSP. The gap 190 may expose the active fin AF of eachactive pattern ACT. The formation of the gap 190 may include removingthe sacrificial gate pattern 110 by performing an etching process havingan etch selectivity with respect to the gate spacers GSP, the firstinterlayer dielectric layer 170, and the etch stop pattern 102 and thenexposing the active fin AF by removing the etch stop pattern 102.

A gate dielectric pattern GI and a gate electrode GE may be formed tofill the gap 190. In detail, a gate dielectric layer may be formed onthe first interlayer dielectric layer 170 to partially fill the gap 190.The gate dielectric layer may be formed to cover the active fin AF. Thegate dielectric layer may include at least one high-k dielectric layer.For example, the gate dielectric layer may include one or more ofhafnium oxide, hafnium silicate, zirconium oxide, and zirconiumsilicate, but embodiments of the present inventive concept are notlimited to these materials. The gate dielectric layer may be formed byperforming, for example, an atomic layer deposition process. A gatelayer may be formed on the gate dielectric layer to fill a remainingportion of the gap 190. The gate layer may include one or more of aconductive metal nitride (e.g., titanium nitride, tantalum nitride,etc.) and a metal e.g., aluminum, tungsten, etc.). The gate dielectriclayer and the gate layer may be planarized to form the gate dielectricpattern GI and the gate electrode GE in the gap 190. The planarizationprocess may expose a top surface of the first interlayer dielectriclayer 170 and top surfaces of the gate spacers GSP. The gate dielectricpattern GI may extend along a bottom surface of the gate electrode GE,and be interposed between the gate electrode GE and the gate spacersGSP.

An upper portion of each of the gate dielectric pattern GI and the gateelectrode GE may be recessed to form a recessed region in the gap 190.The recessed region may expose inner surfaces of the gate spacers GSP. Acapping pattern CAP may be formed to fill the recessed region. Thecapping pattern CAP may cover the recessed top surface of each of thegate dielectric pattern GI and the gate electrode GE, and also cover theexposed inner surfaces of the gate spacers GSP.

A gate structure GS may be defined to include the gate dielectricpattern GI, the gate electrode GE, the capping pattern CAP, and the gatespacers GSP. The substrate 100 may be provided thereon with a pluralityof the gate structures GS horizontally spaced apart from each other. Theplurality of the gate structures GS may include a first gate structureGS1, a second gate structure GS2, a third gate structure GS3, and afourth gate structure GS4 as discussed with reference to FIGS. 2 and 4Ato 4D.

Referring back to FIGS. 2 and 8A to 8D, a second interlayer dielectriclayer 180 may be formed on the first interlayer dielectric layer 170.The second interlayer dielectric layer 180 may include, for example, oneor more of a silicon oxide layer, a silicon nitride layer, a siliconoxynitride layer, and a low-k dielectric layer.

Source/drain contact holes 150H and node contact holes 155H may heformed to penetrate the first and second interlayer dielectric layers170 and 180. The source/drain contact holes 150H and the node contactholes 155H may expose the source/drain regions SD at opposite sides ofeach gate structure GS. Each of the source/drain contact holes 150H mayexpose a corresponding one of the source/drain regions SD. One of thenode contact holes 155H may extend along a top surface of the deviceisolation layer ST so as to expose a corresponding source/drain regionSD on the first NMOSFET region NR1 and a corresponding source/drainregion SD on the PMOSFET region PR. Another of the node contact holes155H may extend along the top surface of the device isolation layer STso as to expose a corresponding source/drain region SD on the secondNMOSFET region NR2 and a corresponding source/drain region SD on thePMOSFET region PR.

The source/drain contact holes 150H and the node contact holes 155H maybe formed by a first exposure process using a first photomask. Theformation of the source/drain contact holes 150H and the node contactholes 155H may include forming a photoresist layer on the secondinterlayer dielectric layer 180 performing the first exposure process onthe photoresist layer to form a photoresist pattern having openings thatdefine areas where the source/drain contact holes 150H and the nodecontact holes 155H are formed, etching the first and second interlayerdielectric layers 170 and 180 using the photoresist pattern as an etchmask, and removing the photoresist pattern. The first photomask maydefine a planar shape of each of the source/drain contact holes 150H andthe node contact holes 155H.

Referring to FIGS. 2 and 9A to 9D, a mask layer (not shown) may beformed on the second interlayer dielectric layer 180 to fill thesource/drain contact holes 150H and the node contact holes 155H. Themask layer (not shown) may be, for example, an SOH layer.

Gate contact holes 160 may he formed on corresponding gate structuresGS. Each of the gate contact holes 160H may penetrate the mask layer andsecond interlayer dielectric layer 180 to expose the gate electrode GEof each gate structure GS. As viewed in plan, one of the gate contactholes 160H, which is provided on the second gate structure GS2, mayoverlap one of the node contact holes 155H. The gate contact hole 160Hon the second gate structure GS2 may be spatially connected to the oneof the node contact holes 155H. As viewed in plan, one of the gatecontact holes 160H, which is provided on the first gate structure GS1,may overlap another of the node contact holes 155H. The gate contacthole 160H on the first gate structure GS1 may be spatially connected tothe other of the node contact holes 155H.

The gate contact holes 160H may be formed by a second exposure processusing a second photomask. The formation of the gate contact holes 160Hmay include forming a photoresist layer on the mask layer, performingthe second exposure process on the photoresist layer to form aphotoresist pattern having openings that define areas where the gatecontact holes 160H are formed, etching the mask layer and the secondinterlayer dielectric layer 180 using the photoresist pattern as an etchmask, and removing the photoresist pattern. The second photomask maydefine a planar shape of each gate contact hole 160H.

Thereafter, the mask layer may be removed. The removal of the mask layermay include performing, for example, an ashing process and/or a stripprocess.

Referring back to FIGS. 2 and 4A to 4D, a conductive layer may be formedon the second interlayer dielectric layer 180 to fill the source/draincontact holes 150H, the node contact holes 155H, and the gate contactholes 160H. The conductive layer may include one or more of a dopedsemiconductor, a metal, and a conductive metal nitride. The conductivelayer may be planarized until the second interlayer dielectric layer 180is exposed, and, thus, source/drain contacts 150 node contacts 155, andgate contacts 160 may be formed respectively in the source/drain contactholes 150H, the node contact holes 155H, and the gate contact holes160H.

The node contacts 155 may include a first node contact 155 a and asecond node contact 155 b. The first node contact 155 a may be connectedto a corresponding source/drain region SD on the first NMOSFET regionNR1 and a corresponding source/drain region SD on the PMOSFET region PR,and may extend onto the device isolation layer ST between the firstNMOSFET region NR1 and the PMOSFET region PR. The second node contact155 b may be connected to a corresponding source/drain region SD on thesecond NMOSFET region NR2 and a corresponding source/drain region SD onthe PMOSFET region PR, and may extend onto the device isolation layer STbetween the second NMOSFET region NR2 and the PMOSFET region PR. Each ofthe node contacts 155 may include, as described with reference to FIG.3, a first end SP1 and a second end EP2 opposite to each other. Thesecond end EP2 may shift from the first end EP1 in a direction (e.g.,the first direction D1) parallel to the top surface of the substrate100. Each of the first node contacts 155 a may have, as viewed in plan,a bent line shape extending in the second direction D2.

Although not shown, the second interlayer dielectric layer 180 may beprovided thereon with electrical lines that are electrically connectedto the source/drain contacts 150 and the gate contacts 160.

FIG. 10 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. FIG. 11 is across-sectional view taken along line II-II′ of FIG. 10. Cross-sectionalviews obtained taken along lines and I-I′, II-II′, III-III′, and IV-IV′of FIG. 10 are substantially the same as FIGS. 4A. 4G, and 4D,respectively. Those parts of the present exemplary embodimentconfigurations that are the same as those of the semiconductor devicesaccording to the foregoing exemplary embodiments described withreference to FIGS. 2. 3, and 4A to 4D are allocated the same referencenumerals thereto. In the present exemplary embodiment that follows,differences from the semiconductor devices according to the foregoingexemplary embodiments described with reference to FIGS. 2, 3, and 4A to4D will be principally explained in the interest of brevity.

Referring to FIGS. 10, 11, and 4C, the first node contact 155 a mayinclude the first end EP1 and the second end EP2 opposite to each other.For example, the first end EP1 may be a portion of the first nodecontact 155 a, which is provided on the first NMOSFET region NR1, andthe second end EP2 may be an another portion of the first node contact155 a, which is provided on the PMOSFET region PR. The first end EP1 maybe spaced apart at the first distance d1 from each of the first andthird gate structures GS1 and GS3, ne second end EP2 may laterally shiftfrom the first end EP1 to lie closer to the second gate structure GS2than to the first gate structure GS1. The second end EP2 may be spacedapart at the second distance d2 from the first gate structure GS1. Insome embodiments, the second end EP2 may be in contact with the secondgate structure GS2. For example, the, second end EP2 may be in contactwith the gate spacer GSP provided on a side of the gate electrode GE ofthe second, gate structure GS2. The second end EP2 may be spaced apartfrom the gate electrode GE of the second gate structure GS2 across thegate spacer GSP (for example, with the gate spacer GSP interleavedtherebetween).

The second node contact 155 b may have a shape symmetrical to that ofthe first node contact 155 a. The second node contact 155 b may includea first end provided on the second NMOSFET region NR2 and a second endprovided on the PMOSFET region PR. The first end of the second nodecontact 155 b may be spaced apart at the first distance d1 from each ofthe second and fourth gate structures GS2 and GS4. The second end of thesecond node contact 155 b may laterally shift from the first end of thesecond node contact 155 b to lie closer to the first gate structure GS1than to the second gate structure GS2. The second end of the second nodecontact 155 b may be spaced apart at the second distance d2 from thesecond gate structure GS2. In some embodiments, the second end of thesecond node contact 155 b may be in contact with the first gatestructure GS1. For example, the second end of the second node contact155 b may be in contact with the gate spacer GSP provided on a side ofthe gate electrode GE of the first gate structure GS1. The second end ofthe second node contact 155 b may be spaced apart from the gateelectrode GE of the first gate structure GS1 across the gate spacer GSP(for example, with the gate spacer GSP interleaved therebetween).

FIG. 12 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. FIG. 13 is across-sectional view taken along line II-II′ of FIG. 12. Cross-sectionalviews obtained taken along lines I-I′, III-III′, and IV-IV′ of FIG. 12are substantially the same as FIGS. 4A, 4C, and 4D, respectively. Thoseparts of the present exemplary embodiment configurations the same asthose of the semiconductor devices according to the foregoing exemplaryembodiments described with reference to FIGS. 2, 3, and 4A to 4B areallocated the same reference numerals thereto. In the present exemplaryembodiment that follows, differences from the semiconductor devicesaccording to the foregoing exemplary embodiments described withreference to FIGS. 2, 3, and 4A to 4D will be principally explained inthe interest of brevity.

Referring to FIGS. 12, 13, and 4C, the first node contact 155 a mayinclude the first end EP1 and the second end EP2 opposite to each other.For example, the first end EP1 may be a portion of the first nodecontact 155 a, which is provided on the first NMOSFET region NR1, andthe second end EP2 may be an another portion of the first node contact155 a, which is provided on the PMOSFET region PR. The first end EP1 maybe spaced apart at the first distance d1 from each of the first andthird gate structures GS1 and GS3. The second end EP2 may laterallyshift from the first end EP1 to lie closer to the second gate structureGS2 than to the first gate structure GS1. The second end EP2 may bespaced apart at the second distance d2 from the first gate structureGS1. In some embodiments, as viewed in plan, the second end EP2 maypartially overlap the second gate structure GS2. The second end EP2 maybe in contact with the gate electrode GE of the second gate structureGS2. For example, the gate electrode GE of the second gate structure GS2may be in contact with the second end EP2 that penetrates the gatespacer GSP provided on a side of the gate electrode GE of the secondgate structure GS2.

The second node contact 155 b may have a shape symmetrical to that ofthe first node contact 155 a. The second node contact 155 b may includea first end provided on the second NMOSFET region NR2 and a second endprovided on the PMOSFET region PR. The first end of the second nodecontact 155 b may be spaced apart at the first distance d1 from each ofthe second and fourth gate structures GS2 and GS4. The second end of thesecond node contact 155 b may laterally shift from the first end of thesecond node contact 155 b to lie closer to the first gate structure GS1than to the second gate structure GS2. The second end of the second nodecontact 155 b may be spaced apart at the second distance d2 from thesecond gate structure GS2. In some embodiments, as viewed in plan, thesecond end of the second node contact 155 b may partially overlap thefirst gate structure GS1. The second end of the second node contact 155b may be in contact with the gate electrode GE of the first gatestructure GS1. For example, the second end of the second node contact155 b may penetrate the gate spacer GSP provided on a side of the gateelectrode GE of the first gate structure GS1 and be in contact with thegate electrode GE of the first gate structure GS1.

According to the exemplary embodiments described with reference to FIGS.10 to 13, the second distance d2 may be maximized. Accordingly, anelectrical short may be reduced, prevented or minimized between eachnode contact 155 and its adjacent gate structures GS.

FIG. 14 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. FIG. 15 is anenlarged view corresponding to section B shown in FIG. 14. FIG. 16 is across-sectional view taken along line V-V′ of FIG. 14. Cross-sectionalviews obtained taken along lines I-I′, II-II′, III-III′ and IV-IV′ ofFIG. 14 are substantially the same as FIGS. 4A, 4B, 4C, and 4D,respectively. Those parts of the present exemplary embodimentconfigurations the same as those of the semiconductor devices accordingto the foregoing exemplary embodiments described with reference to FIGS.2, 3, and 4A to 4D are allocated the same reference numerals thereto. Inthe present exemplary embodiment that follows, differences from thesemiconductor devices according to the foregoing exemplary embodimentsdescribed with reference to FIGS. 2, 3, and 4A to 4D will be principallyexplained in the interest of brevity.

Referring to FIGS. 14, 15, 16, 4B, and 4C, the first node contact 155 amay include the first end EP1 and the second end EP2 opposite to eachother. For example, the first end EP1 may be a portion of the first nodecontact 155 a, which is provided on the first NMOSFET region NR1, andthe second end EP2 may be an another portion of the first node contact155 a, which is provided on the PMOSFET region PR. In some embodiments,the first end EP1 may have a width, which is measured along the firstdirection D1 and decreases with increasing distance from the second endEP2. At least a portion of the first end EP1 may be spaced apart at thefirst distance d1 from each of the first and third gate structures GS1and GS3, and at least another portion of the first end EP1 may he spacedapart at a fourth distance d4 from each of the first and third gatestructures GS1 and GS3. The fourth distance d4 may be measured along thefirst direction D1 and may be greater than the first distance d1. Thesecond end EP2 may laterally shift from the first end EP1, to lie closerto the second gate structure GS2 than to the first gate structure GS1.

The second end EP2 may be spaced apart at the second distance d2 fromthe first gate structure GS1. The fourth distance d4 may be less than orequal to the second distance d2. The second end EP2 may be spaced apartfrom the second gate structure GS2 at the third distance d3, which isless than the first, second, and fourth distances d1, d2, and d4. Thefirst node contact 155 a may have, as viewed in plan, a bent line shapeextending in the second direction D2. For example, as viewed in plan,the first node contact 155 a may have a non-straight line shape CS inwhich at least a portion of the first node contact 155 a is curved toallow the second end EP2 to adjoin the second gate structure GS2. Thewidth of the first end EP1 may continuously or discontinuously decreasewith increasing distance from the second end EP2.

The second node contact 155 b may have a shape symmetrical to that ofthe first node contact 155 a. The second node contact 155 b may includea first end provided on the second NMOSFET region NR2 and a second endprovided on the PMOSFET region PR. In some embodiments, the first end ofthe second node contact 155 b may have a width, which is measured alongthe first direction D1 and decreases with increasing distance from thesecond end of the second node contact 155 b. The second node contact 155b may be configured such that at least a portion of its first end isspaced apart at the first distance d1 from each of the second and fourthgate structures GS2 and GS4 and at least another portion of its firstend is spaced apart at the fourth distance d4 from each of the secondand fourth gate structures GS2 and GS4. The second end of the secondnode contact 155 b may laterally shift from the first end of the secondnode contact 155 b to lie closer to the first gate structure GS1 than tothe second gate structure GS2. The second end of the second node contact155 b may be spaced apart at the second distance d2 from the second gatestructure GS2 and at the third distance d3 from the first gate structureGS1. The second node contact 155 b may have, as viewed in plan, a bentline shape extending in the second direction D2.

FIG. 17 is a plan view illustrating a semiconductor device according toexemplary embodiments of the present inventive concept. Cross-sectionalviews obtained taken along lines I-I′, II-II′, III-III′, and IV-IV′ ofFIG. 17 are substantially the same as FIGS. 4A, 4B, 4C, and 4D,respectively. Those parts of the present exemplar embodimentconfigurations the same as those of the semiconductor devices accordingto the foregoing exemplary embodiments described with reference to FIGS.2, 3, and 4A to 4D are allocated the same reference numerals thereto. Inthe present exemplary embodiment that follows, differences from thesemiconductor devices according to the foregoing exemplary embodimentsdescribed with reference to FIGS. 2, 3, and 4A to 4D will be principallyexplained in the interest of brevity.

Referring to FIG. 17, the active patterns ACT may include an additionalfirst active pattern ACT1_a provided on the second NMOSFET region NR2.The additional first active pattern ACT1_a may be spaced apart from thePMOSFET region PR across the first active pattern ACT1 on the secondNMOSFET region NR2. The second gate structure GS2 may extend in thesecond direction D2 and run across the additional first active patternACT1_a. The gate structures GS may include a fifth gate structure GS5horizontally spaced apart from the first to fourth gate structures GS1to GS4. The fifth gate structure GS5 may he provided on the secondNMOSFET region NR2 and run across the additional first active patternACT1_a. The fifth gate structure GS5 may he aligned in the seconddirection D2 with the first and fourth gate structures GS1 and GS4, andspaced apart in the first direction D1 from the second gate structureGS2.

The source/drain regions SD may include additional source/drain regionsSD provided on the additional first active patterns ACT1_a at oppositesides of each of the second and fifth gate structures GS2 and GS5. Theadditional first active pattern ACT1_a may include an active which isprovided below each of the second and fifth gate structures GS2 and GS5and interposed between the additional source/drain regions SD. A pair ofNMOS transistors may be constituted by the additional first activepattern and the second and fifth gate structures GS2 and G5 extendingacross the additional first active pattern ACT1_a. The first and secondpull-down transistors, the first and second pull-up transistors, and thefirst and second access transistors described with reference to FIGS. 2and 4A to 4D may constitute, together with the pair of NMOS transistorsa dual-port SRAM cell having an isolated read port.

The source/drain contacts 150 may include additional source/draincontacts 150 connected to corresponding additional source/drain regionsSD. Although not shown, the gate contacts 160 may include an additionalgate contact connected to the fifth gate structure GS5.

According to embodiments of the present inventive concept, a nodecontact constituting an SRAM cell may be configured to be adjacent to aspecific gate structure connected to the node contact and to be spacedapart from other adjacent gate structures at desired distances. As aresult, an electrical short may be reduced, prevented or minimizedbetween the node contact and the other adjacent gate structures.Embodiments of the present inventive concept may, therefore, provide asemiconductor device that is suitable for high integration and hasimproved electrical characteristics.

The aforementioned description provides exemplary embodiments forexplaining the present inventive concept. Therefore, the presentinventive concept is not limited to the embodiments described above, andit will be understood by one of ordinary skill in the art thatvariations in form and detail may be made therein without departing fromthe spirit and essential features of the inventive concept.

What is claimed is:
 1. A semiconductor device, comprising: a firstactive pattern and a second active pattern that extend in a firstdirection on a substrate and are spaced apart from each other in asecond direction crossing the first direction; a first gate structurethat extends across the first active pattern and the second activepattern; a second gate structure that is spaced apart from the firstgate structure; and a node contact between the first gate structure andthe second gate structure that electrically connects the first activepattern and the second active pattern to each other, wherein the nodecontact comprises a first end adjacent to the first active pattern and asecond end adjacent to the second active pattern, the second end of thenode contact being shifted in the first direction relative to the firstend of the node contact so as to be closer to the second gate structurethan to the first gate structure.
 2. The semiconductor device of claim1, wherein the first end of the node contact is spaced apart from thefirst gate structure at a first distance, the second end of the nodecontact being spaced apart from the first gate structure at a seconddistance greater than the first distance.
 3. The semiconductor device ofclaim 2, wherein the second end of the node contact is spaced apart fromthe second gate structure at a third distance less than the first andsecond distances.
 4. The semiconductor device of claim 2, furthercomprising a third gate structure that is spaced apart from the firstgate structure across the node contact and extends across the firstactive pattern, wherein the first end of the node contact is spacedapart from the third gate structure at about the first distance.
 5. Thesemiconductor device of claim 1, wherein the node contact has a bentline shape extending in the second direction in a plan view of thesemiconductor device.
 6. The semiconductor device of claim 1, furthercomprising a gate contact on the second gate structure, wherein the gatecontact is connected to the node contact.
 7. The semiconductor device ofclaim 6, wherein the second gate structure is electrically connected tothe first active pattern and the second active pattern through the gatecontact and the node contact.
 8. The semiconductor device of claim 6,wherein the gate contact comprises a same material as that of the nodecontact.
 9. The semiconductor device of claim 6, wherein the contact hasa top surface at a same height as that of a top surface of the nodecontact relative to the substrate.
 10. The semiconductor device of claim1, wherein the first active pattern and the second active pattern havedifferent conductivity types from each other.
 11. The semiconductordevice, comprising: a first active pattern and a second active patternthat extend in a first direction on a substrate and are spaced apartfrom each other in a second direction crossing the first direction; afirst gate structure that extends across the first and second activepatterns; and a node contact on a side of the first gate structure thatelectrically connects the first active pattern and the second activepattern to each other, wherein the node contact comprises a first endadjacent to the first active pattern and a second end adjacent to thesecond active pattern, the first end of the node contact being spacedapart from the first gate structure, at a first distance, and the secondend of the node contact being spaced apart from the first gate structureat a second distance greater than the first distance.
 12. Thesemiconductor device of claim 11, wherein the node contact has a bentline shape, the node contact and the first gate structure extending inthe second direction in a plan view of the semiconductor device.
 13. Thesemiconductor device of claim 11, further comprising a second gatestructure that is spaced apart from the first gate structure across thenode contact and partially overlaps the second active pattern, whereinthe second end of the node contact is positioned closer to the secondgate, structure than to the first gate structure.
 14. The semiconductordevice of claim 13, further comprising a third gate structure that isspaced apart from the first gate structure across the node contact andextends across the first active pattern, wherein a pitch between thefirst and second gate structures is the same as a pitch between thefirst and third gate structures.
 15. The semiconductor device of claim14, wherein the first end of the node contact is spaced apart from thethird gate structure at about the first distance.
 16. A semiconductordevice, comprising: a first gate structure on a substrate; a second gatestructure spaced apart in a first direction from the first gatestructure; and a third gate structure spaced apart in the firstdirection fro, the first gate structure; a node contact between thefirst gate structure and the second gate structure and between the firstgate structure and the third gate structure; wherein the second gatestructure and the third gate structure are aligned with each other in asecond direction crossing the first direction, and wherein the nodecontact comprises a first end between the first structure and the thirdgate structure and a second end between the first gate structure and thesecond gate structure, the second end of the node contact being shifted,in the first direction relative to the first end of the node contact soas to be closer to the second gate structure than to the first gatestructure.
 17. The semiconductor device of claim 16, wherein at least aportion of the node contact extends in parallel to the first gatestructure and the third gate structure.
 18. The semiconductor device ofclaim 16, wherein the second gate structure comprises a gate electrodeon the substrate and a gate spacer on a sidewall, of the gate electrode,and the second end of the node contact is spaced apart from the gateelectrode across the gate spacer.
 19. The semiconductor device of claim18, further comprising a gate contact connected to the gate electrode ofthe second gate structure, wherein the gate contact is connected to thenode contact, and wherein the gate electrode of the second gatestructure is electrically connected to the substrate through the gatecontact and the node contact.
 20. The semiconductor device of claim 19,wherein the gate contact. and the node contact have respective topsurfaces at a same height relative to the substrate.